86x86 1/43 LS9929
86x86, 1/43 scan, LS9929, rcvbp
Download
Module
entry
- file
- config/panels/mined/86x86-43s-ls9929.toml
- status
- generates
- origin
- mined
- vendor files
- 4
- agreement
- 0.67
- vendors
- Colorlight
- examples
- P1.86-9929+9739-172x688.rcvbp P1.86-9929+9739-344x344.rcvbp p1.86-9929+9739-172x688.rcvbp
chip
- name
- LS9929 (mined)
- library
- config/chips/mined/ls9929.toml
spec
- name
- 86x86-43s-ls9929
module
- width
- 86
- height
- 86
- scan
- 43
- line_dir
- 0
- data_groups
- 1
- serial_clock
- 12
screen
- width
- 86
- height
- 86
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 86
boot
- arm_at_boot
- true
Timing
current
- gains
- [43, 43, 43, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/86x86-43s-ls9929.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "86x86-43s-ls9929" [meta] status = "generates" origin = "mined" sources = 4 agreement = 0.67 examples = ["P1.86-9929+9739-172x688.rcvbp", "P1.86-9929+9739-344x344.rcvbp", "p1.86-9929+9739-172x688.rcvbp"] vendors = ["Colorlight"] [module] width = 86 height = 86 scan = 43 line_dir = 0 data_groups = 1 serial_clock = 12 [screen] width = 86 height = 86 [chip] library = "config/chips/mined/ls9929.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 86 [boot] arm_at_boot = true