16x128 1/64 SM16389
16x128, 1/64 scan, SM16389, rcvbp
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Module
entry
- file
- config/panels/mined/16x128-64s-sm16389.toml
- status
- generates
- origin
- mined
- vendor files
- 7
- agreement
- 1
- vendors
- Colorlight
- examples
- P1.25-256x128-64S-16389+2018-V8.1.rcvbp CD-P1.2-256X128-SM16389+SM5368-64S-DC-8.85.rcvbp CD-P1.2-256X128-SM16389+32020-64S-DC-8.85.rcvbp
chip
- name
- SM16389 (mined)
- library
- config/chips/mined/sm16389.toml
spec
- name
- 16x128-64s-sm16389
module
- width
- 16
- height
- 128
- scan
- 64
- line_dir
- 0
- data_groups
- 0
- serial_clock
- 7
screen
- width
- 16
- height
- 128
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 16
boot
- arm_at_boot
- true
Timing
current
- gains
- [43, 43, 43, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/16x128-64s-sm16389.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "16x128-64s-sm16389" [meta] status = "generates" origin = "mined" sources = 7 agreement = 1.00 examples = ["P1.25-256x128-64S-16389+2018-V8.1.rcvbp", "CD-P1.2-256X128-SM16389+SM5368-64S-DC-8.85.rcvbp", "CD-P1.2-256X128-SM16389+32020-64S-DC-8.85.rcvbp"] vendors = ["Colorlight"] [module] width = 16 height = 128 scan = 64 line_dir = 0 data_groups = 0 serial_clock = 7 [screen] width = 16 height = 128 [chip] library = "config/chips/mined/sm16389.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 16 [boot] arm_at_boot = true