16x104 1/52 DP5525

Panels

16x104, 1/52 scan, DP5525, rcvbp

Download

Module

16x104 1/52

entry

file: config/panels/mined/16x104-52s-dp5525.toml
status: generates
origin: mined
vendor files: 13
agreement: 1
vendors: Colorlight
examples: Q1.5S12B52(3265+32020)-V3-W1.rcvbp P1.53-208x104-52S-75接口-3265+2018,2018-S.1对开.rcvbp P1.53-208x104-52S-75接口-3265+2018,2018-S.1.rcvbp

chip

name: DP5525 (mined)
library: config/chips/mined/dp5525.toml

Wiring

spec

parse error: cannot parse value: "P1.53-208x104-52S-75\u63a5\u53e3-3265+2018

Timing

config/panels/mined/16x104-52s-dp5525.toml

# generated by scripts/corpus-mine.py; regenerate rather than edit

name = "16x104-52s-dp5525"

[meta]
status = "generates"
origin = "mined"
sources = 13
agreement = 1.00
examples = ["Q1.5S12B52(3265+32020)-V3-W1.rcvbp", "P1.53-208x104-52S-75\u63a5\u53e3-3265+2018,2018-S.1\u5bf9\u5f00.rcvbp", "P1.53-208x104-52S-75\u63a5\u53e3-3265+2018,2018-S.1.rcvbp"]
vendors = ["Colorlight"]

[module]
width = 16
height = 104
scan = 52
line_dir = 0
data_groups = 0
serial_clock = 10

[screen]
width = 16
height = 104

[chip]
library = "config/chips/mined/dp5525.toml"

[current]
gains = [43, 43, 43, 43]
percent = [0.1, 0.1, 0.1]

[mapping]
reversed_groups = true
reversed_lines = false
block = 16

[boot]
arm_at_boot = true