160x80 1/40 SM16380

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Module

Wiring

Timing

config/panels/160x80-40s-sm16380.toml

# generated by scripts/corpus-mine.py; regenerate rather than edit

name = "160x80-40s-sm16380"

[meta]
status = "derived"
sources = 13
agreement = 1.00
examples = ["Q2AC40(16380+5368)-V3.7.rcvbp", "Q2AC40(16380+5158)-V3.7-W1.rcvbp", "P2-160x80-40S-16380+2018,5566,5368-V6.2.rcvbp"]
vendors = ["Colorlight"]
notes = "Values are the majority across 13 vendor configuration files, 100% of the files for this module class. Never driven on a bench. The pixel map has 6400 entries; the block-7 image builder packs at most 4096, so `rxp config gen` writes the .rcvbp but not the boot image."

[module]
width = 160
height = 80
scan = 40
line_dir = 0
data_groups = 1
serial_clock = 15

[screen]
width = 160
height = 80

[chip]
library = "config/chips/sm16380.toml"

[current]
gains = [43, 43, 43, 43]
percent = [0.1, 0.1, 0.1]

[mapping]
reversed_groups = true
reversed_lines = false
block = 160

[boot]
arm_at_boot = true