160x80 1/40 SM16380
160x80, 1/40 scan, SM16380, rcvbp
Download
Module
entry
- file
- config/panels/mined/160x80-40s-sm16380.toml
- status
- generates
- origin
- mined
- vendor files
- 13
- agreement
- 1
- vendors
- Colorlight
- examples
- Q2AC40(16380+5368)-V3.7.rcvbp Q2AC40(16380+5158)-V3.7-W1.rcvbp P2-160x80-40S-16380+2018,5566,5368-V6.2.rcvbp
- notes
- the pixel map has 6400 entries; the block-7 image builder packs at most 4096, so `rxp config gen` writes the .rcvbp but not the boot image
chip
- name
- SM16380 (mined)
- library
- config/chips/mined/sm16380.toml
Wiring
spec
- parse error
- cannot parse value: "P2-160x80-40S-16380+2018
Timing
config/panels/mined/160x80-40s-sm16380.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "160x80-40s-sm16380" [meta] status = "generates" origin = "mined" sources = 13 agreement = 1.00 examples = ["Q2AC40(16380+5368)-V3.7.rcvbp", "Q2AC40(16380+5158)-V3.7-W1.rcvbp", "P2-160x80-40S-16380+2018,5566,5368-V6.2.rcvbp"] vendors = ["Colorlight"] notes = "the pixel map has 6400 entries; the block-7 image builder packs at most 4096, so `rxp config gen` writes the .rcvbp but not the boot image" [module] width = 160 height = 80 scan = 40 line_dir = 0 data_groups = 1 serial_clock = 15 [screen] width = 160 height = 80 [chip] library = "config/chips/mined/sm16380.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 160 [boot] arm_at_boot = true