128x64 1/16 DP5525
128x64, 1/16 scan, DP5525, rcvbp
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Module
entry
- file
- config/panels/mined/128x64-16s-dp5525.toml
- status
- generates
- origin
- mined
- vendor files
- 8
- agreement
- 1
- vendors
- Colorlight
- examples
- Q2.5AB16(3256+32019)-V1.2-W1.rcvbp Q2.5AB16(3264+32019)-W1.rcvbp Q2.5AB16(3264+2013)-W1.rcvbp
chip
- name
- DP5525 (mined)
- library
- config/chips/mined/dp5525.toml
spec
- name
- 128x64-16s-dp5525
module
- width
- 128
- height
- 64
- scan
- 16
- line_dir
- 0
- data_groups
- 1
- serial_clock
- 10
screen
- width
- 128
- height
- 64
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 128
boot
- arm_at_boot
- true
Timing
current
- gains
- [43, 43, 43, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/128x64-16s-dp5525.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "128x64-16s-dp5525" [meta] status = "generates" origin = "mined" sources = 8 agreement = 1.00 examples = ["Q2.5AB16(3256+32019)-V1.2-W1.rcvbp", "Q2.5AB16(3264+32019)-W1.rcvbp", "Q2.5AB16(3264+2013)-W1.rcvbp"] vendors = ["Colorlight"] [module] width = 128 height = 64 scan = 16 line_dir = 0 data_groups = 1 serial_clock = 10 [screen] width = 128 height = 64 [chip] library = "config/chips/mined/dp5525.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 128 [boot] arm_at_boot = true