104x104 1/52 LS9929
104x104, 1/52 scan, LS9929, rcvbp
Download
Module
entry
- file
- config/panels/mined/104x104-52s-ls9929.toml
- status
- generates
- origin
- mined
- vendor files
- 9
- agreement
- 0.9
- vendors
- Colorlight
- examples
- p3.07-104x52-52S-9929+9739-5.0(104x416)-75B.rcvbp p3.07-104x52-52S-9929+9739-5.0(208x208folio)-75B.rcvbp p3.07-104x52-52S-9929+9739-5.0-75B.rcvbp
- notes
- the pixel map has 5408 entries; the block-7 image builder packs at most 4096, so `rxp config gen` writes the .rcvbp but not the boot image
chip
- name
- LS9929 (mined)
- library
- config/chips/mined/ls9929.toml
spec
- name
- 104x104-52s-ls9929
module
- width
- 104
- height
- 104
- scan
- 52
- line_dir
- 0
- data_groups
- 0
- serial_clock
- 10
screen
- width
- 104
- height
- 104
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 104
boot
- arm_at_boot
- true
Timing
current
- gains
- [43, 43, 43, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/104x104-52s-ls9929.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "104x104-52s-ls9929" [meta] status = "generates" origin = "mined" sources = 9 agreement = 0.90 examples = ["p3.07-104x52-52S-9929+9739-5.0(104x416)-75B.rcvbp", "p3.07-104x52-52S-9929+9739-5.0(208x208folio)-75B.rcvbp", "p3.07-104x52-52S-9929+9739-5.0-75B.rcvbp"] vendors = ["Colorlight"] notes = "the pixel map has 5408 entries; the block-7 image builder packs at most 4096, so `rxp config gen` writes the .rcvbp but not the boot image" [module] width = 104 height = 104 scan = 52 line_dir = 0 data_groups = 0 serial_clock = 10 [screen] width = 104 height = 104 [chip] library = "config/chips/mined/ls9929.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 104 [boot] arm_at_boot = true