Colorlight E120
identity
- name
- E120
- vendor
- Colorlight
- family
- colorlight
- id
- 0x64
- status
- tested
- file
- config/cards/e120.toml
- image pattern
- E320_PWM_FPGA{version}_*.hex
- sdram staging
- true
- specification
- specification
- notes
- Specification: E120 Specification V1.1.0, held at third-party/datasheets/Colorlight_E120_Receiving_Card_Specification.pdf and published at https://support.colorlightinside.com/uploads/E120_Receiving_Card_Specification_V1.1.0_1763194995.pdf, linked from https://en.colorlightinside.com/service/download/?cat=602 (the host answers 403 without a Referer from that page). The published copy is a later typesetting of the same V1.1.0, not the same bytes; the control area, the HUB75 J1~J12 count and the two gigabit RJ45 ports read the same in both. Gateware builds are named E320: one line for the whole classic family (third-party/README.md). Every address in [memory] was dumped from this card (docs/fpga/flash-layout.md), not inferred.
limits
- max width
- 1024 px
- max height
- 192 px
- hub ports
- 12
memory map
- block bytes
- 0x10000
- primary bank
- 0x000000, 0x0b0000 bytes, 11 blocks
- golden bank
- 0x200000
- parameter block
- 0x07 (block 7)
- eeprom mirror
- 0x07f000
- guarded from 16.53
- 0x00, 0x01, 0x02, 0x08
boot image offsets
- basic_pack
- 0x0000
- data_swap
- 0x0500
- module_positions
- 0x0600
- chip_page
- 0x0900
- void_line
- 0x1000
- void_line_columns
- 0x1400
- anti_void
- 0x1800
- mapping
- 0x3000
- scan_table
- 0x6000
- rcvbp
- 0x8000
- map_entries
- 4096
- rcvbp_max
- 0x6ffc
Tested panels
| panel | spec | firmware | version |
|---|---|---|---|
| P2.5 128x64 1/16 SM16269S | config/panels/p25-128x64-sm16269s.toml | E320_PWM_FPGA16.53_20231227_SM16386S_SM16269SH.hex | 16.53 |
Firmware
129 images with their versions, driver chips and checksums.
- E320_PWM_FPGA16.53_20231227_SM16386S_SM16269SH.hex (16.53)driven with P2.5 128x64 1/16 SM16269S